1. Field of the Invention
The present invention relates to a level detection device and method, especially to a clock edge detection device and method.
2. Description of Related Art
A general electronic circuit needs a reference clock for its individual elements operating properly or different elements functioning synchronously. Said reference clock is usually generated by a frequency synthesizer with a source clock. In order to make sure that the level high and level low durations of the reference clock are the same for preventing malfunction, the frequency synthesizer is supposed to generate the reference clock of 50% duty cycle. However, due to the limitation such as manufacturing process variation, the frequency synthesizer is likely to generate a reference clock having the duty cycle other than 50%. Moreover, in consideration of the limited design resources, the frequency synthesizer might lack for a preinstalled calibration function to correct the duty cycle. Therefore, in view of the problem caused by process variation and the cost-effective issue about design resources, a solution capable of detecting the duty cycle of a reference clock is desired, which is supposed to be capable of determining the influence caused by process variation or the like and then providing the analysis for clock skew calibration or future design reference.
Those interested in more detail of the prior art references may refer to the following documents: U.S. Pat. No. 6,671,652, U.S. Pat. No. 7,400,555, and U.S. Pat. No. 7,403,055.